Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Error (10170): Verilog HDL syntax error at nios_system_inst.v

Hello all, I got the following error while trying the Introduction to the Altera SOPC Builder Using Verilog Design SOPC Tutorial. I'm using Quartus II 10.0 . I'm lost on figuring it out. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Please do not multipost, it won't get you more answers.

Regarding the error, as already said in the thread an *_inst.v file is just an instantiation example and shouldn't be compiled as is in a project. Remove the file from the project and copy/paste its contents in a top level file if necessary.