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Altera_Forum
Honored Contributor
Honored ContributorError (10170): Verilog HDL syntax error at nios_system_inst.v
Hello all, I got the following error while trying the Introduction to the Altera SOPC Builder Using Verilog Design SOPC Tutorial. I'm using Quartus II 10.0 . I'm lost on figuring it out. ...
Altera_ForumHonored Contributor
Honored Contributorthe _inst.v is just an example Verilog instance. you'll need to drop it into a module and port map it
