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Altera_Forum
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14 years ago

Error (10170): Verilog HDL syntax error at nios_system_inst.v

Hello all, I got the following error while trying the Introduction to the Altera SOPC Builder Using Verilog Design SOPC Tutorial. I'm using Quartus II 10.0 . I'm lost on figuring it out. ...
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Altera_Forum
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14 years ago

I can't see anything wrong with syntax. I am only not sure about where the error is since it says it is located at nios_system_inst.v and this may not mean the code you are showing. I wonder why the file name is same as instant name.