Honored Contributor
Honored ContributorMaybe I should rephrase the question. I have a dual processor NiosI system on my custom board that I would like to port to NiosII and would like some pointers.
Currently the main Nios_0 is the "main" cpu and Nios_1 is a small secondary processor that acts as a high priority IRQ handler and pre-processor. Nios_0 runs and resets at the beginning of 16MB of sdram. (the only external mem in the system) Nios_1 runs and resets in a 10K chunk of on-chip ram. Each processor has a very small but separate chunk of on chip ram that holds its vtable. Another small piece of on chip ram acts as a "mailbox" for the two processors to talk through, but bulk data is processed in sdram buffers. In deciding how to port to NiosII and the bootloader, it is not apparent the best settings for Reset and Exception addresses for the two processors. Do I reset to the epcs_controller or sdram? Can the epcs_controller be the reset for both processors? Can the sdk handle both processor running out of sdram? (at different offsets) Are there any multi-processors examples available that demonstrate the features I require? Are there any pointers for making use of more that 60% of the onchip ram? (I had inched up to 78% on my NiosI system) Any help would be appreciated. We've been at this for some time now and everthing always works in isolation, (USB, streaming, processing, realtime IRQ) but putting together the final commercial quality system is proving elusive. Thanks, Ken
