Honored Contributor
Honored ContributorThanks for the response, I 've been trying a different approach from the hps side but still no luck and that's why I haven't been able to reply sooner.
I've attached an image displaying how sdram controller, dma controller, and onchip are interfaced. I have both the onchip memory and sdram connected to the data master of the nios. When I try to increase the number of bytes to be transferred, I start getting incorrect bytes when reading back the data to verify. This is my biggest issue because I need to be able to write to the sdram at a min of 32MB/sec. I'll have to look into using signal tap because I've never used it. I use the alt_nticks(), maybe I need to be using something else? --- Quote Start --- I am not very familiar with Nios-DMA designs. So do be patient with me. How is the connection between the onchip-memory-DMA-SDRAM? Is there any sharing of onchip memory/SDRAM with Nios? You can try to signal tap and see whether transactions at the onchip/SDRAM interface is ok, ie continuous transfer or back-pressure at the interface and root cause the back-pressure. Can you increase the size of the bytes sent? Just to get better average compared to smaller data bytes that can be highly affected by overhead. How did you come up with the 2MB/sec? Do you have timer/performance counter? --- Quote End ---
