Forum Discussion
Altera_Forum
Honored Contributor
9 years agoFor some reason I can't get at the file too. But I agree with derim, if you break the image processing down to small portions of the frame you might be able to get a lot of speedup.
The reason why I was asking earlier if you can process the data as a stream is if you instantiate the blocks inside the mSGDMA (dispatcher, read master, and write master) you can perform a memory to memory transfer with your hardware accelerator between the read and write master if the number of bytes into the block = number of bytes coming out. If there isn't a balance between the amount of input data and output you would need use two DMAs so that can control them differently. This is what I mean by transform + transfer type of operations: HPS SDRAM --> DMA read master --> Your video transform logic --> DMA write master --> HPS SDRAM With a topology like that the operation just looks like a memory movement to the system. It's also self scheduling because the DMA won't write the result to memory until they have been processed which makes scheduling much simpler.