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Altera_Forum's avatar
Altera_Forum
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8 years ago

device tree source ehternet and skew timing => performance issue ?

hello, i ve some problem with the network performance and the cyclone 5 on linux. i try different kernel versions, after some error research i found the solution, it was/is the ethernet skew. ...
Altera_Forum's avatar
Altera_Forum
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7 years ago

Hello roll3,

I stumbled over the same question. So how to find/calculate the correct PHY skew settings? I found the following two sources which deals with the topic:

1.“Cyclone V and Arria V SoC Device Design Guideline -> Board Design Guideline for SoC FPGAs -> Design Guideline for HPS Interfaces -> HPS EMAC PHY Interface: https://www.altera.com/documentation/doq1481305867183.html#fvj1481304448658

2. KSZ9031RNX Datasheet -> 3.9.3 RGMII PAD SKEW REGISTERS: http://ww1.microchip.com/downloads/en/devicedoc/00002117f.pdf

So the skew settings depends on the used MAC (here Cyclone V), the board traces (your layout) and the PHY (here the KSZ9031). However, I did not figure out how to apply the given information correctly. Do you have newer information about the topic?

Best regards,

niosIIuser