Device Tree - Registering IRQ in Linux GIC

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Hello everyone.

I've done some design using Qsys and I'm trying to get my Device Tree to work. I took the *.dtb from GHRD and changed to a *.dts (so I would be able to modify it as I wish).

Also, I generated the device tree through sopc2dts (I guess this is the command) and the *.dtb file it generates doesn't boot my board, so something is getting messed up. What I did in order to solve the problem is the following: I took the IPs that are are inside the

hps_0_bridges: bridge@c0000000

and I put the IPs that I use in my qsys design.

  
         msgdma@0x100000000 {   
               compatible = "altr,msgdma-15.0", "altr,msgdma-1.0";
                reg = <0x00000001 0x00000000 0x00000020>,
                         <0x00000001 0x00000020 0x00000010>;
                reg-names = "CSR", "Descriptor_Slave";
                interrupt-parent = <&hps_0_arm_gic_0>;
                interrupts = <0 43 4>;
                clocks = <&clk_0>;
            }; 
    hps_0_arm_gic_0: intc@fffed000 {
        compatible = "arm,cortex-a9-gic-15.0", "arm,cortex-a9-gic";
       # interrupt-cells = <3>;
        interrupt-controller;
        reg = <0xfffed000 0x1000 0xfffec100 0x100>;
        reg-names = "axi_slave0", "axi_slave1";
        linux,phandle = <0x2>;
        phandle = <0x2>;
    };

The thing is I can't register the interrupt 43 onto GIC... (I only checked the proc/interrupts file)

https://alteraforum.com/forum/attachment.php?attachmentid=13492&stc=1

Anyone knows what might be causing the problem? Currently I can use all my peripherals from lw and my fpga2sdram bus. This mSGDMA writes to the ARM SDRAM, and the design works well, but I can't get this IRQ thing to work.

Thanks in advance!

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For those who might be struggling with the same stuff... I have developed a device driver which runs some come in the kernel that deals with the hardware from FPGA.