Device drivers under niosII IDE

Nios II software developer's handbook says "The HAL provides the C-language macros IORD and IOWR that expand to the appropriate assembly instructions to bypass the data cache. The IORD macro expands to the ldwio instruction, and the IOWR macro expands to the stwio instruction." And Nios II processor reference handbook says "When using instruction ldw/ldwio, the effective byte address must be word aligned. If the byte address is not a multiple of 4, the operation is undefined." But the definition of macros IORD and IOWR in altera_avalon_uart_regs.h of Nios II IDE cann't guarantee the byte address is a multiple of 4. How to explain? And the slave read & write transfer on avalon bus has multiple timing, then how the macros IORD & IOWR to use the read & write timing? Thanks.