Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Design works with NIOS II/e, not II/f

I have a design in whch I read ADC samples from PIO with a dual clock FIFO input and transport the output data with SGDMA to on-chip memory. It took me a few days of experimenting to discover ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

I am sorry for being not more specific. In this case I meant that

I did not get the expected results. I got constant values in stead

of noisy ADC values.

I ran the design with the USBblaster connected, so that was o.k.