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Altera_Forum
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9 years ago

Design works with NIOS II/e, not II/f

I have a design in whch I read ADC samples from PIO with a dual clock FIFO input and transport the output data with SGDMA to on-chip memory. It took me a few days of experimenting to discover ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Hi Bhaumik,

Thanks for your suggestion. I will try it and report the result.

Best regards,

Jos