Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Design works with NIOS II/e, not II/f

I have a design in whch I read ADC samples from PIO with a dual clock FIFO input and transport the output data with SGDMA to on-chip memory. It took me a few days of experimenting to discover ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Hello Jos,

One possible cause for this is DATA CACHE. Search for this on google and you would be able to find some good information regarding this. As a quick check, reduce DATA CACHE memory to 0 when you configure Nios II/f in your Qsys system.

Warm Regards,

Bhaumik