DE2 board SRAM interface

Hello there,

I'm trying to implement a simple system in DE2 board and I want to use external SRAM for my application. I have followed the following steps but still it doesn't work.

I looked many similar old posts but can't figure out my problem. Any help/ suggestion is appreciated.

1. Added a SRAM component IDT71V416 SRAM 512KB (256K x 16 bit). The SRAM in DE2 board is IS61LV25616AL. Guess it is a 256K x 16-bit SRAM.

2. Added a Avalon MM Tristate bridge.

3. Connected SRAM to Avalon Tristate Master.

4. I'm using only one external 50MHz clock which is common for both CPU and Tristate bridge.

5. Generated the nios_system and added top level where I weld the component connections to the FPGA pins.

address_to_the_sram_0 (18 downto 1) => SRAM_ADDR(17 downto 0),

be_n_to_the_sram_0(0) => SRAM_LB_N,

be_n_to_the_sram_0(1) => SRAM_UB_N,

data_to_and_from_the_sram_0 (15 downto 0) => SRAM_DQ,

read_n_to_the_sram_0=> SRAM_OE_N,

select_n_to_the_sram_0 =>SRAM_CE_N,

write_n_to_the_sram_0 => SRAM_WE_N

Now, when try to run I'm getting the following error:

Downloading 00080000 ( 0%)

Downloaded 53KB in 0.9s (58.8KB/s)

Verifying 00080000 ( 0%)

Verify failed between address 0x80000 and 0x8D2FF

Leaving target processor paused

My questions:

1. I find from previous posts where people have suggested to an interface between bridge and external SRAM using components editor. But I have simply fused the bridge connections to the external SRAM believing it is suffice. Is my understanding right? Is it really required to have an interface between the tristate bridge and the external SRAM pins?

2. Am I missing anything related to timing?

Thanks!