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Altera_Forum
Honored Contributor
8 years agode10 nano ethernet phy clock loanio
Hi everybody, I'm working on an implementation of openpowerlink (http://openpowerlink.sourceforge.net/web/openpowerlink/documentation.html) for the de10-nano platform. The powerlink fpga code ne...
Altera_Forum
Honored Contributor
8 years ago --- Quote Start --- I remember seeing some sort of similar issues if I implement SignalTap inside the design. If you have SignalTap, try removing that and see if that helps. If not, try using one of the clocks that are generated from the HPS itself (User Clock 0 or 1) --- Quote End --- I'm not using signal tap. I tried using the HPS clocks aswell, same fitter error. I ended up using a clock divider instead of the pll.