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Altera_Forum's avatar
Altera_Forum
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14 years ago

DE0-NIOS2 clock speed limit 50MHZ

Hi, have "problem". I have DE0 dev board. When I load NIOS2 to fpga and use 50MHz from on board sorce. It works. When I try to add pll 50MHz - > works. But if I use more then 50MHz (pll ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Hi,

I think I have solved the problem. I used in sdc file "derive_pll_clocks -create_base_clocks" instead off manual pll creation and it works. 275 fmax (in qsys I have left cpu +pll +sysid + clock_in.

Thank you for replay's guys.