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Altera_Forum's avatar
Altera_Forum
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14 years ago

DE0-NIOS2 clock speed limit 50MHZ

Hi, have "problem". I have DE0 dev board. When I load NIOS2 to fpga and use 50MHz from on board sorce. It works. When I try to add pll 50MHz - > works. But if I use more then 50MHz (pll ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

In Timequest, have a look at the top failing paths. It will give you an indication on what parts to optimize to increase the fmax. In some SOPC systems you need to add some pipeline bridges on the critical paths.

Using the timing advisor (Tools menu) will also give you indications on what parameters you can change to increase the fmax.