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Altera_Forum's avatar
Altera_Forum
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14 years ago

DE0-NIOS2 clock speed limit 50MHZ

Hi, have "problem". I have DE0 dev board. When I load NIOS2 to fpga and use 50MHz from on board sorce. It works. When I try to add pll 50MHz - > works. But if I use more then 50MHz (pll ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Hi,

it doesn't only depend of the NIOS2 core but of all what's driven by this clock.

Did you use the pll compensation for that clock ?

on the pll megawizard : "1 Paramter settings - General/Modes - which output clock will be compensated for ?"

Then, if you have a big archietcture, you can split it on different clock domains depending on your critical path, so that the cpu clock can be raised higher.