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Altera_Forum's avatar
Altera_Forum
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14 years ago

DE0-NIOS2 clock speed limit 50MHZ

Hi, have "problem". I have DE0 dev board. When I load NIOS2 to fpga and use 50MHz from on board sorce. It works. When I try to add pll 50MHz - > works. But if I use more then 50MHz (pll ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Hi,

Thanks for fast reply.

Yes, fmax limit to 60mhz. But I use f type core, 4 level pipeline.

Could different type of pll resolve the problem????

Report gives me note : limi due to high minimum pulse width violation (tcl)