Honored Contributor
Honored ContributorAN736 talks about EPCQ, not EPCS.
Couple days ago, I found UG-20001 Generic Nios II Booting Methods User Guide. And on page 11 it has a section about "Nios II Processor Application Copied from EPCS Flash to RAM Using Boot Copier". "The EPCS address space is not mapped into the Altera Avalon EPCS Flash Controller’s Avalon MM slave interface. Instead, read or write accesses are done through CSRs. Upon system reset, the EPCS device needs to be initialized before usage. For these reasons, the EPCS controller-based boot copier is required for initializing the EPCS device and copying the Nios II application to RAM for execution. The EPCS controller instantiates a block of boot ROM internally at its base address (offset 0x0, just before EPCS controller’s CSRs) for storing the boot copier. Nios II reset vector offset must set to EPCS controller base address, such that upon system reset the boot copier is executed first to initialize the EPCS controller and device." So the reset vector memory should set to EPCS controller and the reset vector offset should set to 0x00. I still don't know what I have done wrong.
