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New ContributorDDR3 SDRAM Controller with UniPHY Genaration Error
Info: drr: Variation language : Verilog Info: drr: Output directory : C:\intelFPGA_lite\21.1\DDR Info: drr: Generating variation file C:\intelFPGA_lite\21.1\DDR\drr.v Info: drr: Generating synthesis files <html>Info: Generating <b>altera_mem_if_ddr3_emif</b> "<b>drr</b>" for QUARTUS_SYNTH <html>Info: "<b>drr</b>" instantiated <b>altera_mem_if_ddr3_emif</b> "<b>drr</b>" <html>Info: "<b>drr</b>" instantiated <b>altera_mem_if_ddr3_pll</b> "<b>pll0</b>" Info: Generating clock pair generator Info: Generating drr_p0_altdqdqs Info: Info: ***************************** Info: Info: Remember to run the drr_p0_pin_assignments.tcl Info: script after running Synthesis and before Fitting. Info: Info: ***************************** Info: <html>Info: "<b>drr</b>" instantiated <b>altera_mem_if_ddr3_phy_core</b> "<b>p0</b>" <html>Info: "<b>drr</b>" instantiated <b>altera_mem_if_ddr3_afi_mux</b> "<b>m0</b>" Error: Error during execution of "{C:/intelfpga_lite/21.1/quartus//../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally Error: Execution of command "{C:/intelfpga_lite/21.1/quartus//../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt" failed Error: /mnt/c/intelfpga_lite/21.1/quartus/bin64/uniphy_mcc.exe -ac_code sequencer_mc/ac_rom.s -inst_code sequencer_mc/inst_rom.s -ac_rom ../drr_s0_AC_ROM.hex -inst_rom ../drr_s0_inst_ROM.hex -header sequencer/sequencer_auto.h -vheader ../sequencer_auto_h.sv -ac_rom_init sequencer/sequencer_auto_ac_init.c -inst_rom_init sequencer/sequencer_auto_inst_init.c -DAC_ROM_USER_ADD_0=0_0000_0000_0000 -DAC_ROM_USER_ADD_1=0_0000_0000_1000 -DAC_ROM_MR0=0001000110001 -DAC_ROM_MR0_CALIB= -DAC_ROM_MR0_DLL_RESET=0001100110000 -DAC_ROM_MR1=0000000000000 -DAC_ROM_MR1_OCD_ENABLE= -DAC_ROM_MR2=0000000001000 -DAC_ROM_MR3=0000000000000 -DAC_ROM_MR0_MIRR=0001001001001 -DAC_ROM_MR0_DLL_RESET_MIRR=0001011001000 -DAC_ROM_MR1_MIRR=0000000000000 -DAC_ROM_MR2_MIRR=0000000010000 -DAC_ROM_MR3_MIRR=0000000000000 -DQUARTER_RATE=0 -DHALF_RATE=1 -DFULL_RATE=0 -DNON_DES_CAL=0 -DAP_MODE=0 -DGUARANTEED_READ_BRINGUP_TEST=0 -DMEM_ADDR_WIDTH=13 -DHARD_PHY=0 Error: UniPHY Sequencer Microcode Compiler Error: Copyright (C) 2021 Intel Corporation. All rights reserved. Error: Info: Reading sequencer_mc/ac_rom.s ... Error: Info: Reading sequencer_mc/inst_rom.s ... Error: Info: Writing ../drr_s0_AC_ROM.hex ... Error: Info: Writing ../drr_s0_inst_ROM.hex ... Error: Info: Writing sequencer/sequencer_auto_ac_init.c ... Error: child process exited abnormally Error: Cannot find sequencer/sequencer.elf <html>Error: An error occurred<br> while executing<br>"error "An error occurred""<br> (procedure "_error" line 8)<br> invoked from within<br>"_error "Cannot find $seq_file""<br> ("if" then script line 2)<br> invoked from within<br>"if {[file exists $seq_file] == 0} {<br> _error "Cannot find $seq_file"<br> }"<br> (procedure "alt_mem_if::util::seq_mem_size::get_max_memory_usage" line 14)<br> invoked from within<br>"alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequencer" "sequencer.elf""<br> invoked from within<br>"set calc_mem_size [alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequencer" "sequencer.elf"]]"<br> ("if" then script line 2)<br> invoked from within<br>"if { !$do_only_rw_mgr_mc && !($bfm_mode || $hps_mode)} {<br> set calc_mem_size [alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequenc..."<br> (procedure "generate_qsys_sequencer_sw" line 943)<br> invoked from within<br>"generate_qsys_sequencer_sw $prepend_str $protocol $pre_compile_dir $fileset $inhdl_dir $rdimm $lrdimm 0 0 $nios_hex_file_name $ac_rom_init_file_name ..."<br> invoked from within<br>"set seq_mem_size_list [generate_qsys_sequencer_sw $prepend_str $protocol $pre_compile_dir $fileset $inhdl_dir $rdimm $lrdimm 0 0 $nios_hex_file_name ..."<br> ("if" else script line 2)<br> invoked from within<br>"if {[::alt_mem_if::util::qini::qini_value alt_mem_if_seq_size_request 0] > 0} {<br> set seq_mem_size [::alt_mem_if::util::qini::qini_value alt_mem_if_se..."<br> (procedure "alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer" line 238)<br> invoked from within<br>"alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer "${name}" $protocol $tmpdir $fileset {}"<br> invoked from within<br>"set qsys_sequencer_files_list [alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer "${name}" $protocol $tmpdir $fileset {}]"<br> (procedure "alt_mem_if::gen::uniphy_gen::generate_sequencer_files" line 3)<br> invoked from within<br>"alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "DDR3" $tmpdir QUARTUS_SYNTH"<br> invoked from within<br>"foreach generated_file [alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "DDR3" $tmpdir QUARTUS_SYNTH] {<br> set file_name [file tail $genera..."<br> (procedure "generate_synth" line 8)<br> invoked from within<br>"generate_synth drr_s0" <html>Info: "<b>drr</b>" instantiated <b>altera_mem_if_ddr3_qseq</b> "<b>s0</b>" Error: Generation stopped, 5 or more modules remaining <html>Info: Done "<b>drr</b>" with 11 modules, 33 files Info: drr: Generating example design <html>Info: Generating <b>altera_mem_if_ddr3_emif</b> "<b>drr</b>" for EXAMPLE_DESIGN Info: Generating simulation example design Info: Generating synthesizable example design Error: Error during execution of script generate_ed.tcl: s0: Error during execution of "{C:/intelfpga_lite/21.1/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally Error: Error during execution of script generate_ed.tcl: s0: Execution of command "{C:/intelfpga_lite/21.1/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt" failed Error: Error during execution of script generate_ed.tcl: s0: /mnt/c/intelfpga_lite/21.1/quartus/bin64/uniphy_mcc.exe -ac_code sequencer_mc/ac_rom.s -inst_code sequencer_mc/inst_rom.s -ac_rom ../drr_example_if0_s0_AC_ROM.hex -inst_rom ../drr_example_if0_s0_inst_ROM.hex -header sequencer/sequencer_auto.h -vheader ../sequencer_auto_h.sv -ac_rom_init sequencer/sequencer_auto_ac_init.c -inst_rom_init sequencer/sequencer_auto_inst_init.c -DAC_ROM_USER_ADD_0=0_0000_0000_0000 -DAC_ROM_USER_ADD_1=0_0000_0000_1000 -DAC_ROM_MR0=0001000110001 -DAC_ROM_MR0_CALIB= -DAC_ROM_MR0_DLL_RESET=0001100110000 -DAC_ROM_MR1=0000000000000 -DAC_ROM_MR1_OCD_ENABLE= -DAC_ROM_MR2=0000000001000 -DAC_ROM_MR3=0000000000000 -DAC_ROM_MR0_MIRR=0001001001001 -DAC_ROM_MR0_DLL_RESET_MIRR=0001011001000 -DAC_ROM_MR1_MIRR=0000000000000 -DAC_ROM_MR2_MIRR=0000000010000 -DAC_ROM_MR3_MIRR=0000000000000 -DQUARTER_RATE=0 -DHALF_RATE=1 -DFULL_RATE=0 -DNON_DES_CAL=0 -DAP_MODE=0 -DGUARANTEED_READ_BRINGUP_TEST=0 -DMEM_ADDR_WIDTH=13 -DHARD_PHY=0 Error: Error during execution of script generate_ed.tcl: s0: UniPHY Sequencer Microcode Compiler Error: Error during execution of script generate_ed.tcl: s0: Copyright (C) 2021 Intel Corporation. All rights reserved. Error: Error during execution of script generate_ed.tcl: s0: Info: Reading sequencer_mc/ac_rom.s ... Error: Error during execution of script generate_ed.tcl: s0: Info: Reading sequencer_mc/inst_rom.s ... Error: Error during execution of script generate_ed.tcl: s0: Info: Writing ../drr_example_if0_s0_AC_ROM.hex ... Error: Error during execution of script generate_ed.tcl: s0: Info: Writing ../drr_example_if0_s0_inst_ROM.hex ... Error: Error during execution of script generate_ed.tcl: s0: Info: Writing sequencer/sequencer_auto_ac_init.c ... Error: Error during execution of script generate_ed.tcl: s0: child process exited abnormally Error: Error during execution of script generate_ed.tcl: s0: Cannot find sequencer/sequencer.elf Error: Error during execution of script generate_ed.tcl: s0: An error occurred Error: Error during execution of script generate_ed.tcl: Generation stopped, 8 or more modules remaining Error: Execution of script generate_ed.tcl failed Error: ERROR: Cannot find sequencer/sequencer.elf Error: 2022.01.24.10:49:04 Info: Error: ******************************************************************************************************************** Error: Error: Use qsys-generate for a simpler command-line interface for generating IP. Error: Error: Run ip-generate with switch --remove-qsys-generate-warning to prevent this notice from appearing in subsequent runs. Error: Error: ******************************************************************************************************************** Error: 2022.01.24.10:49:16 Warning: drr_example: ODT is disabled. Enabling ODT (Mode Register 1) may improve signal integrity Error: 2022.01.24.10:49:16 Warning: drr_example: 'Quick' simulation modes are NOT timing accurate. Some simulation memory models may issue warnings or errors Error: 2022.01.24.10:49:16 Warning: drr_example.if0.pll_bridge: pll_bridge.pll_sharing cannot be both connected and exported Error: 2022.01.24.10:49:16 Warning: drr_example.if0: if0.pll_sharing must be exported, or connected to a matching conduit. Error: 2022.01.24.10:49:16 Info: drr_example: Generating alt_mem_if_ddr3_tg_ed "drr_example" for QUARTUS_SYNTH Error: 2022.01.24.10:49:18 Info: Interconnect is inserted between master d0.avl and slave if0.avl because the master has address signal 30 bit wide, but the slave is 26 bit wide. Error: 2022.01.24.10:49:24 Info: if0: "drr_example" instantiated altera_mem_if_ddr3_emif "if0" Error: 2022.01.24.10:49:25 Info: d0: "drr_example" instantiated altera_avalon_mm_traffic_generator "d0" Error: 2022.01.24.10:49:25 Info: mm_interconnect_0: "drr_example" instantiated altera_mm_interconnect "mm_interconnect_0" Error: 2022.01.24.10:49:25 Info: rst_controller: "drr_example" instantiated altera_reset_controller "rst_controller" Error: 2022.01.24.10:49:26 Info: pll0: "if0" instantiated altera_mem_if_ddr3_pll "pll0" Error: 2022.01.24.10:49:26 Info: p0: Generating clock pair generator Error: 2022.01.24.10:49:27 Info: p0: Generating drr_example_if0_p0_altdqdqs Error: 2022.01.24.10:49:33 Info: p0: Error: 2022.01.24.10:49:33 Info: p0: ***************************** Error: 2022.01.24.10:49:33 Info: p0: Error: 2022.01.24.10:49:33 Info: p0: Remember to run the drr_example_if0_p0_pin_assignments.tcl Error: 2022.01.24.10:49:33 Info: p0: script after running Synthesis and before Fitting. Error: 2022.01.24.10:49:33 Info: p0: Error: 2022.01.24.10:49:33 Info: p0: ***************************** Error: 2022.01.24.10:49:33 Info: p0: Error: 2022.01.24.10:49:33 Info: p0: "if0" instantiated altera_mem_if_ddr3_phy_core "p0" Error: 2022.01.24.10:49:33 Info: m0: "if0" instantiated altera_mem_if_ddr3_afi_mux "m0" Error: 2022.01.24.10:49:35 Error: s0: Error during execution of "{C:/intelfpga_lite/21.1/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally Error: 2022.01.24.10:49:35 Error: s0: Execution of command "{C:/intelfpga_lite/21.1/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt" failed Error: 2022.01.24.10:49:35 Error: s0: /mnt/c/intelfpga_lite/21.1/quartus/bin64/uniphy_mcc.exe -ac_code sequencer_mc/ac_rom.s -inst_code sequencer_mc/inst_rom.s -ac_rom ../drr_example_if0_s0_AC_ROM.hex -inst_rom ../drr_example_if0_s0_inst_ROM.hex -header sequencer/sequencer_auto.h -vheader ../sequencer_auto_h.sv -ac_rom_init sequencer/sequencer_auto_ac_init.c -inst_rom_init sequencer/sequencer_auto_inst_init.c -DAC_ROM_USER_ADD_0=0_0000_0000_0000 -DAC_ROM_USER_ADD_1=0_0000_0000_1000 -DAC_ROM_MR0=0001000110001 -DAC_ROM_MR0_CALIB= -DAC_ROM_MR0_DLL_RESET=0001100110000 -DAC_ROM_MR1=0000000000000 -DAC_ROM_MR1_OCD_ENABLE= -DAC_ROM_MR2=0000000001000 -DAC_ROM_MR3=0000000000000 -DAC_ROM_MR0_MIRR=0001001001001 -DAC_ROM_MR0_DLL_RESET_MIRR=0001011001000 -DAC_ROM_MR1_MIRR=0000000000000 -DAC_ROM_MR2_MIRR=0000000010000 -DAC_ROM_MR3_MIRR=0000000000000 -DQUARTER_RATE=0 -DHALF_RATE=1 -DFULL_RATE=0 -DNON_DES_CAL=0 -DAP_MODE=0 -DGUARANTEED_READ_BRINGUP_TEST=0 -DMEM_ADDR_WIDTH=13 -DHARD_PHY=0 Error: 2022.01.24.10:49:35 Error: s0: UniPHY Sequencer Microcode Compiler Error: 2022.01.24.10:49:35 Error: s0: Copyright (C) 2021 Intel Corporation. All rights reserved. Error: 2022.01.24.10:49:35 Error: s0: Info: Reading sequencer_mc/ac_rom.s ... Error: 2022.01.24.10:49:35 Error: s0: Info: Reading sequencer_mc/inst_rom.s ... Error: 2022.01.24.10:49:35 Error: s0: Info: Writing ../drr_example_if0_s0_AC_ROM.hex ... Error: 2022.01.24.10:49:35 Error: s0: Info: Writing ../drr_example_if0_s0_inst_ROM.hex ... Error: 2022.01.24.10:49:35 Error: s0: Info: Writing sequencer/sequencer_auto_ac_init.c ... Error: 2022.01.24.10:49:35 Error: s0: child process exited abnormally Error: 2022.01.24.10:49:35 Error: s0: Cannot find sequencer/sequencer.elf Error: 2022.01.24.10:49:35 Error: s0: An error occurred Error: while executing Error: "error "An error occurred"" Error: (procedure "_error" line 8) Error: invoked from within Error: "_error "Cannot find $seq_file"" Error: ("if" then script line 2) Error: invoked from within Error: "if {[file exists $seq_file] == 0} { Error: _error "Cannot find $seq_file" Error: }" Error: (procedure "alt_mem_if::util::seq_mem_size::get_max_memory_usage" line 14) Error: invoked from within Error: "alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequencer" "sequencer.elf"" Error: invoked from within Error: "set calc_mem_size [alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequencer" "sequencer.elf"]]" Error: ("if" then script line 2) Error: invoked from within Error: "if { !$do_only_rw_mgr_mc && !($bfm_mode || $hps_mode)} { Error: set calc_mem_size [alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequenc..." Error: (procedure "generate_qsys_sequencer_sw" line 943) Error: invoked from within Error: "generate_qsys_sequencer_sw $prepend_str $protocol $pre_compile_dir $fileset $inhdl_dir $rdimm $lrdimm 0 0 $nios_hex_file_name $ac_rom_init_file_name ..." Error: invoked from within Error: "set seq_mem_size_list [generate_qsys_sequencer_sw $prepend_str $protocol $pre_compile_dir $fileset $inhdl_dir $rdimm $lrdimm 0 0 $nios_hex_file_name ..." Error: ("if" else script line 2) Error: invoked from within Error: "if {[::alt_mem_if::util::qini::qini_value alt_mem_if_seq_size_request 0] > 0} { Error: set seq_mem_size [::alt_mem_if::util::qini::qini_value alt_mem_if_se..." Error: (procedure "alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer" line 238) Error: invoked from within Error: "alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer "${name}" $protocol $tmpdir $fileset {}" Error: invoked from within Error: "set qsys_sequencer_files_list [alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer "${name}" $protocol $tmpdir $fileset {}]" Error: (procedure "alt_mem_if::gen::uniphy_gen::generate_sequencer_files" line 3) Error: invoked from within Error: "alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "DDR3" $tmpdir QUARTUS_SYNTH" Error: invoked from within Error: "foreach generated_file [alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "DDR3" $tmpdir QUARTUS_SYNTH] { Error: set file_name [file tail $genera..." Error: (procedure "generate_synth" line 8) Error: invoked from within Error: "generate_synth drr_example_if0_s0" Error: 2022.01.24.10:49:35 Info: s0: "if0" instantiated altera_mem_if_ddr3_qseq "s0" Error: 2022.01.24.10:49:35 Error: Generation stopped, 8 or more modules remaining Error: 2022.01.24.10:49:35 Info: drr_example: Done "drr_example" with 17 modules, 38 files Info: Creating Quartus project <html>Info: Done "<b>drr</b>" with 1 modules, 51 files Info: drr: Generating simulation model <html>Info: Generating <b>altera_mem_if_ddr3_emif</b> "<b>drr</b>" for SIM_VERILOG <html>Info: "<b>drr</b>" instantiated <b>altera_mem_if_ddr3_emif</b> "<b>drr</b>" <html>Info: "<b>drr</b>" instantiated <b>altera_mem_if_ddr3_pll</b> "<b>pll0</b>" Info: Generating clock pair generator Info: Generating drr_p0_altdqdqs <html>Info: "<b>drr</b>" instantiated <b>altera_mem_if_ddr3_phy_core</b> "<b>p0</b>" <html>Info: "<b>drr</b>" instantiated <b>altera_mem_if_ddr3_afi_mux</b> "<b>m0</b>" Error: Error during execution of "{C:/intelfpga_lite/21.1/quartus//../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally Error: Execution of command "{C:/intelfpga_lite/21.1/quartus//../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt" failed Error: /mnt/c/intelfpga_lite/21.1/quartus/bin64/uniphy_mcc.exe -ac_code sequencer_mc/ac_rom.s -inst_code sequencer_mc/inst_rom.s -ac_rom ../drr_s0_AC_ROM.hex -inst_rom ../drr_s0_inst_ROM.hex -header sequencer/sequencer_auto.h -vheader ../sequencer_auto_h.sv -ac_rom_init sequencer/sequencer_auto_ac_init.c -inst_rom_init sequencer/sequencer_auto_inst_init.c -DAC_ROM_USER_ADD_0=0_0000_0000_0000 -DAC_ROM_USER_ADD_1=0_0000_0000_1000 -DAC_ROM_MR0=0001000110001 -DAC_ROM_MR0_CALIB= -DAC_ROM_MR0_DLL_RESET=0001100110000 -DAC_ROM_MR1=0000000000000 -DAC_ROM_MR1_OCD_ENABLE= -DAC_ROM_MR2=0000000001000 -DAC_ROM_MR3=0000000000000 -DAC_ROM_MR0_MIRR=0001001001001 -DAC_ROM_MR0_DLL_RESET_MIRR=0001011001000 -DAC_ROM_MR1_MIRR=0000000000000 -DAC_ROM_MR2_MIRR=0000000010000 -DAC_ROM_MR3_MIRR=0000000000000 -DQUARTER_RATE=0 -DHALF_RATE=1 -DFULL_RATE=0 -DNON_DES_CAL=0 -DAP_MODE=0 -DGUARANTEED_READ_BRINGUP_TEST=0 -DMEM_ADDR_WIDTH=13 -DHARD_PHY=0 Error: UniPHY Sequencer Microcode Compiler Error: Copyright (C) 2021 Intel Corporation. All rights reserved. Error: Info: Reading sequencer_mc/ac_rom.s ... Error: Info: Reading sequencer_mc/inst_rom.s ... Error: Info: Writing ../drr_s0_AC_ROM.hex ... Error: Info: Writing ../drr_s0_inst_ROM.hex ... Error: Info: Writing sequencer/sequencer_auto_ac_init.c ... Error: child process exited abnormally Error: Cannot find sequencer/sequencer.elf <html>Error: An error occurred<br> while executing<br>"error "An error occurred""<br> (procedure "_error" line 8)<br> invoked from within<br>"_error "Cannot find $seq_file""<br> ("if" then script line 2)<br> invoked from within<br>"if {[file exists $seq_file] == 0} {<br> _error "Cannot find $seq_file"<br> }"<br> (procedure "alt_mem_if::util::seq_mem_size::get_max_memory_usage" line 14)<br> invoked from within<br>"alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequencer" "sequencer.elf""<br> invoked from within<br>"set calc_mem_size [alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequencer" "sequencer.elf"]]"<br> ("if" then script line 2)<br> invoked from within<br>"if { !$do_only_rw_mgr_mc && !($bfm_mode || $hps_mode)} {<br> set calc_mem_size [alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequenc..."<br> (procedure "generate_qsys_sequencer_sw" line 943)<br> invoked from within<br>"generate_qsys_sequencer_sw $prepend_str $protocol $pre_compile_dir $fileset $inhdl_dir $rdimm $lrdimm 0 0 $nios_hex_file_name $ac_rom_init_file_name ..."<br> invoked from within<br>"set seq_mem_size_list [generate_qsys_sequencer_sw $prepend_str $protocol $pre_compile_dir $fileset $inhdl_dir $rdimm $lrdimm 0 0 $nios_hex_file_name ..."<br> ("if" else script line 2)<br> invoked from within<br>"if {[::alt_mem_if::util::qini::qini_value alt_mem_if_seq_size_request 0] > 0} {<br> set seq_mem_size [::alt_mem_if::util::qini::qini_value alt_mem_if_se..."<br> (procedure "alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer" line 238)<br> invoked from within<br>"alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer "${name}" $protocol $tmpdir $fileset {}"<br> invoked from within<br>"set qsys_sequencer_files_list [alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer "${name}" $protocol $tmpdir $fileset {}]"<br> (procedure "alt_mem_if::gen::uniphy_gen::generate_sequencer_files" line 3)<br> invoked from within<br>"alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "DDR3" $tmpdir SIM_VERILOG"<br> invoked from within<br>"foreach generated_file [alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "DDR3" $tmpdir SIM_VERILOG] {<br> set file_name [file tail $generate..."<br> (procedure "generate_verilog_sim" line 7)<br> invoked from within<br>"generate_verilog_sim drr_s0" <html>Info: "<b>drr</b>" instantiated <b>altera_mem_if_ddr3_qseq</b> "<b>s0</b>" Error: Generation stopped, 5 or more modules remaining <html>Info: Done "<b>drr</b>" with 11 modules, 25 files Info: Generated simulation scripts for Modelsim in C:/intelFPGA_lite/21.1/DDR/drr_sim/mentor directory. Info: Generated simulation scripts for VCS and VCS MX in C:/intelFPGA_lite/21.1/DDR/drr_sim/synopsys directory. Info: Generated simulation scripts for NCSIM in C:/intelFPGA_lite/21.1/DDR/drr_sim/cadence directory. Info: Generated simulation scripts for Riviera-PRO in C:/intelFPGA_lite/21.1/DDR/drr_sim/aldec directory.
Hello,
I am trying to use DDR3 SDRAM Controller with UniPHY Intel FPGA IP 21.1. My Quartus version is 21.1 Lite. When genarating IP using IP Catalog I got the this error. My oparating system is Win10 64bit 21H2(OS Build 19044.1466).
I´m using Ubuntu 18.04 and WSL version 1. I also tried with version Ubuntu 20.4 and I got same error. Also I tried with and without example project generation.
Thanks for your help.
Övgü
Best
