DDR SDRAM won't fit!

Hi All,

I am using a cyclone III starter kit, which has the EP3C25F324C6 FPGA on and the zentel A3S56D40ETP-G5 SD-RAM.

I have (i think) added the DDR ram controller in QSYS correctly (I used the information in the system architect design tutorial, which I appreciate s for the NEEK).

I then generated the system and all is OK, no warnings and no errors. I then dropped this into a quartus schematic, connected all the IO to the outputs and bidirectionals. I then did analysis and elaboration which went OK but when I try to compile the project i get some nasty erros the chief of which are:

Error (171000): Can't fit design in device.

I find this hard to believe as there is nothing else in the system to speak of!

also I get:

Error (165024): The DQ group with DQS pin "MEMDQS[1]" has invalid DQ group assignements.

Error (165024): The DQ group with DQS pin "MEMDQS[0]" has invalid DQ group assignements.

I am a little puzzled to say the least.

If someone could shed some light on this for me I would be most grateful.

D