DDR Critical Warning

Hi again,

I suppouse there is no easy answer for these critical warnings.

For trying to guest a solution I suggest to explain each error.

If someone can contribute I 'll be grateful.

The first one:

"the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL"

When I attach the ddr controller into the sopc system, the clock wich feeds the component is the external clk connected to niosII. In my design this clock comes from another PLL. I have read that in cycloneIII there are no neighboring PLLs, is that true?

The second one:

"must have bandwidth mode set to High instead of Medium"

The ddr controller pll has auto mode in the bandwith option. I suppouse when I work with devices which have a speed grade of 8, it is no possible for the system to implement high bandwith, am I right?

The third one:

"Timing requirements not met"

When I use the timing analyzer, the top failing paths belong to the clock crossing bridge, has something to do with the two errors commented above?

The fourth one:

"Read Capture and Write timing analyses may not be valid"

No idea from where start.

Many thanks!

ifdm