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Honored ContributorDDR_afi_clk to PLL input ?
Hello,
My scenario: I've a project with a DDR2 SDRAM controller, this controller gives me two clocks : .ddr2.afi_clk = 200 Mhz and .ddr2.afi_half_clk = 100 Mhz, I use the afi_half_clock for some blocks on my SOPC but I need others slower clocks to other blocks. I've tried to connect the afi_half_clk to the input of other PLL but i get this error from Quartus: " must be driven by a non-inverted input pin or another PLL, optionally through a Clock Control block" I also tried to use the Global_clock_control_block with the input been the alf_half_clock and the out put to the PLL. Questions: [LIST] Do I need to use the afi clock when I use the SDRAM memory controller? [/LIST] [LIST] How do I use the afi clock on the Input of a PLL block to all clocks be synchronous ? [/LIST] [LIST] Can I use Avalon Memory clock corssing bridge with no synchronized clocks ? [/LIST] Thanks, Rafael C.1 Reply
Altera_Forum--- Quote Start --- [LIST] Do I need to use the afi clock when I use the SDRAM memory controller? [/LIST] Rafael C. --- Quote End --- I'm not 100% sure about this one, but as the AFI (Altera PHY Interface) is provided to make it easier to interface with external memory, I would say that yes, you do need to use it. I'm assuming that by bundling it all up Altera relieves you of having to define all the tricky timing settings. --- Quote Start --- [LIST] How do I use the afi clock on the Input of a PLL block to all clocks be synchronous ? [/LIST] Rafael C. --- Quote End --- I have found PLLs and clock control modules to be a real headache, as often you are only allowed to connect certain inputs with certain outputs. By the looks of it afi_half_clk is inverted - is it possible to export the non-inverted one? --- Quote Start --- [LIST] Can I use Avalon Memory clock corssing bridge with no synchronized clocks ? [/LIST] Rafael C. --- Quote End --- The clocks of clock crossing bridges do not need to be synchronised.
