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Julien
Occasional Contributor
Occasional ContributorCycloneV SoC : NIOS2 mSGDMA transfers failing above 2047 bytes ?
Hi, I have a design for CycloneV SoC (DE0 Nano SoC board) that includes a NIOS2/e, transferring data to the HPS' DDR3 memory over the f2h_sdram interface, via an adress span expander, using an mSGDM...
JulienOccasional Contributor
Occasional ContributorI went a little further: if I go through the f2h_axi_slave bridge of the HPS instead of the f2h_sdram, the DMA transfer works correctly at 2048 bytes (and above, up to 4096 bytes which is the limit I set).
Any idea why using the (faster) f2h_sdram would specifically fail above 2047 bytes / what setting in the f2h_sdram I might have missed ?
