Honored Contributor
Honored ContributorHello Franz,
first of all I'm sorry for the following "stupid" questions :oops:. My intention is to bridge the JTAG interface of the FPGA with the CFI interface of the flash memory. To cut a long story short, I want to create a PFL with a sopc system (in Qsys). Thus I want to write configuration data (.sof) to the flash memory. Every power-on the FPGA should configure from flash memory. But why do I need a .elf? For booting? Your solution sounds quite simple. Could you please explain it more detailed, because I didn't get everything. I would appreciate if you can explain it step by step. I even don't know, how to start the command shell?! I have just one more question. First I have to build a sopc system, generate it and instantiate it (e.g. with a .bdf) in my quartus project. Then I assign all pins, set all Dual-Purpose Pins to regular I/O and set configuration to Passive Serial (to get no "can't place multiple pins assigned to pin location...errors during compilation). Next, I compile my project and donwload the .sof to the FPGA. Now I'm able to program my flash memory with the command shell. Is that all right? Or did I misunderstand sth.?
