Cyclone V SPI master releases chip select when TX FIFO runs empty. HOW TO PREVENT???

I am not sure what you mean by enabling the CS because there is no such control in the SPI.

Do you mean setting the slave to select in the SER register?

If so, this does not directly lower the CS.

It's the controller that will drive the 4 CS lines with the inverse of the SER register when the transfer is started.

The CS goes low When the first frame is written in the TX FIFO and stays low until the FIFO is empty.

It's explained in the handbook (SPI master section / data transfer subsection:

The SPI master starts data transfers when all the following conditions are met:

■ The SPI master is enabled

■ There is at least one valid entry in the transmit FIFO buffer

■ A slave device is selected

What are you checking when polling?

The FIFO level, or the status register bit indicating the TX FIFO empty, or the one indicating the TX FIFO full?

If you are sending less than 256 frames there are no needs to do any check.

Do non-stop writes, the FIFO will absorb all the data.