Cyclone V SPI master releases chip select when TX FIFO runs empty. HOW TO PREVENT???

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The CS getting de-selected when the TX FIFO becomes empty is as expected.

In the Cyclone V Handbook Vol# 3, SPI section (19) in the "Master SPI and SSI transfer" sub-section:

when the transfer mode is “transmit and receive” or “transmit only” (tmod = 0 or

tmod = 1, respectively), transfers are terminated by the shift control logic when the

transmit fifo buffer is empty. for continuous data transfers, you must ensure that the

transmit fifo buffer does not become empty before all the data have been

transmitted.

The only real "work-around" is:

you must ensure that the transmit fifo buffer does not become empty before all the data have been transmitted.

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Hi Eric, thanks for the reply. I tried, polling method. Filled the TX FIFO with 32 bytes and then enabled the chip select. But still I am seeing chip select to toggle after each byte in cscope. I am using Arria10 and linux kernel.

I would like to transfer a byte and read two bytes in the same transfer. I also tried filling TX FIFO, while reading RX data. TX FIFO level remained non-zero, but still CS toggled in scope.