Cyclone V SPI master releases chip select when TX FIFO runs empty. HOW TO PREVENT???

Thanks for the replay sunshine!

I have seen that trick, but it does not solve my problem. By testing that workaround, it looked like Altera defines a transaction as transmitting all bytes in the FIFO until it runs empty. Which is exactly my problem. The default, without the workaround is toggling CS for every byte...

I found a solution which is not only working for Cyclone V, but is also supported by the generic part of the SPI driver in Linux.

It's as simple as using GPIO as CS.

I simply pull down GPIO CS giving me all the time in the world to enable the HW SPI master, fill upp the FIFO. Finally select a CS controlled by the SPI Master, which is either an unused HPS pin or is terminated in the FPGA.

The SPI FIFO can run empty many times, while I decide when to release the GPIO CS.