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Altera_Forum
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8 years ago

Cyclone V SOC F2S Arbitration

Hello, In my Cyclone V SOC device I have an F2S bridge implemented to facilitate memory sharing between the FPGA and HPS. The base address I'm using is 0x30000000. The FPGA writes images to...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Got an IP that writes the data to a big buffer (currently we are using a ramp to validate the data movement) and the data is not consistent.

My device driver tells the IP we want data and the IP freezes the buffer and interrupts the driver. When I do the copy_to_user and check the data there are inconsistencies. I check the data in the device driver and it shows the same problem (ruled out the 'copy_to_user').

Some evaluation boards it works fine others it doesn't.

Really hard to think our custom board is going to be successful when we can't get consistencies with eval boards and the same code and device driver that is so simple.