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Altera_Forum
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9 years ago

Cyclone V SOC 256 bit F2S

Hello, My design has a F2S_SDRAM bus between the FPGA to HPS. The current bus is set to 128 bits. I see however that it can be configured to be as wide as is 256 bits. Question: ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

I suspect the interface is not enabled yet. By default the F2S port should be held in reset internally until enabled. Are you using the HPS linux driver to configure the FPGA, I think enabling the F2S and bridges is something it does for you. In the example you referenced you'll probably find a section of code that enables the necessary FPGA interfaces if you want to see which registers those are.