Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorCyclone V SOC 256 bit F2S
Hello, My design has a F2S_SDRAM bus between the FPGA to HPS. The current bus is set to 128 bits. I see however that it can be configured to be as wide as is 256 bits. Question: ...
Altera_ForumHonored Contributor
Honored ContributorHi BadOmen,
I'm running a Linux OS with the bit file generated from a design modified from https://www.altera.com/support/support-resources/design-examples/soc/fpga-to-hps-bridges-design-example.html. I have a problem with the F2S interface. When I manually start a DMA transfer, I see the read request is asserted to the interface but no readdata/readdatavalid come back. Did I miss anything? Thank you so much!
