Cyclone V SOC 256 bit F2S

The main reason to use a 256-bit port is to get more bandwidth with less clock speed, or that you don't have two 128-bit masters in your system to merit two ports. Multiple ports is handy when you need to perform traffic shaping such as giving one port more priority than the other but if you are just looking for raw throughput a 256-bit port operating at 100MHz will use up all the memory bandwidth assuming you have an efficient master hooked up to it on the FPGA side of the device.

You might find the Cyclone V SoC design here useful to see the effects of burst length has on the FPGA to HPS ports of the device: https://www.altera.com/support/support-resources/design-examples/soc/fpga-to-hps-bridges-design-example.html As you can see once you have a 256-bit F2S interface you don't really even need to use a bursting master because the traffic that goes off-chip gets downsized into SDRAM size bursts.