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Honored Contributor
Honored ContributorCyclone V SOC 256 bit F2S
Hello, My design has a F2S_SDRAM bus between the FPGA to HPS. The current bus is set to 128 bits. I see however that it can be configured to be as wide as is 256 bits. Question: ...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Did you face something like this? --- Quote End --- Yes, I had to make a new pre-loader from the hand-off configuration files. It didn't work prior to this.
