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Honored Contributor
Honored ContributorCyclone V SOC 256 bit F2S
Hello, My design has a F2S_SDRAM bus between the FPGA to HPS. The current bus is set to 128 bits. I see however that it can be configured to be as wide as is 256 bits. Question: ...
Altera_ForumHonored Contributor
Honored ContributorI tried to use the F2S once but I could not do it. I used the F2H bridge instead.
I was not using linux or other operating system, but baremetal. I saw some examples for the F2S using the baremetal but it was using some kind of an assembly file that was used for initializing the F2S bridge. Did you face something like this? My F2H clock was 100MHz. The transfer speed by using one DMA inside the FPGA was around 1 Giga Byte for reading from the DDR3 to the FPGA. F2H bit width of transfer was 128 bits.
