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Honored Contributor
Honored ContributorCyclone V SOC 256 bit F2S
Hello, My design has a F2S_SDRAM bus between the FPGA to HPS. The current bus is set to 128 bits. I see however that it can be configured to be as wide as is 256 bits. Question: ...
Altera_ForumHonored Contributor
Honored ContributorNo,
I didn't try it. For 2 reasons: 1. The 128 bit version (with burst lenght = 8) gives me more than enough bandwidth. 2. The time domain that communicates with the F2S clocks @ 120MHz. If I double the width to 256 I'm almost certain that it won't meet timing.
