Altera_ForumHonored Contributor8 years agoCyclone V, sharing memory between FPGA and HPS Hello. I'm using de0-nano-SoC and want FPGA and HPS to have access to the same memory. I use GHRD as base project. In Qsys I have activated "enable in-system memory content editor" to see how it work...Show More
Altera_ForumHonored Contributor8 years agoIs there any way to read data on FPGA side which was written by HPS (trough h2f axi port)?
Recent DiscussionsError generating BSPSolvedNIOS V/m dbg_reset_out signal (Q25.1 Std, MAX10)SolvedWhere is FreeRTOS-Plus-TCP DesignSolvedNIOS-V QSYS Warning Properties (associatedClock) have been set onSolvedDK-DEV-AGI027-RA: JTAG chain broken after Nios V Hello, FPGA recovery fails