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Don't understand what you are trying to achieve. Are you using the FPGA PLL with a succeeding DDS frequency divider as before? Then you'll get of course the usual DDS jitter of one DDS input clock cycle.
According to the parameters in your code, you are using integer PLL mode. It generates - by nature - an output clock with no systematic jitter, but some phase noise which might be inappropriate for high performance applications. But surely better than DDS. Integer PLL is however limited to M/(N*C) frequency ratios.
Alternatively you could use PLL in fractional mode. Fractional PLL operation is also introducing jitter, but less than DDS.
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I'm trying to achieve 0.01% jitter of the target clock rate, if possible. I've tried integer mode and fractional (not quite clear on how to calculate the fractional part without the spreadsheet). Both integer mode and fractional have the same jitter at 7MHz. I would expect better performance, so I assume I'm doing something wrong.
Is there a benefit to running the PLL internal frequency at a higher rate? Say by setting the M-counter at a higher value, then using other ratios to bring the output rate back down?
That's what I'm asking, is there a bias towards setting the M, N, C, k values for best performance? Some stand alone clock synthesizer ICs have rules about the order in which variables are chosen and why. Stability, jitter, etc.
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