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The PLL setup has the exact same jitter profile as a stand alone counter.
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Don't understand what you are trying to achieve. Are you using the FPGA PLL with a succeeding DDS frequency divider as before? Then you'll get of course the usual DDS jitter of one DDS input clock cycle.
According to the parameters in your code, you are using integer PLL mode. It generates - by nature - an output clock with no systematic jitter, but some phase noise which might be inappropriate for high performance applications. But surely better than DDS. Integer PLL is however limited to M/(N*C) frequency ratios.
Alternatively you could use PLL in fractional mode. Fractional PLL operation is also introducing jitter, but less than DDS.
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