Cyclone 5 pcie example project failure

Unfortunately, I am not really sure what could be the root cause of your issue. I have a slightly different setup (Quartus 16.0 lite version, Windows 10) - from the design downloaded the link below:

https://releases.rocketboards.org/release/2015.10/pcie-ed/hw/

I manage to open Qsys and run "Generate HDL.." successfully for both the full design and the simple design (no modification was done on either .qsys file). I chose the HDL design files as "Verilog" and Simulation Model as "None".

Just to confirm, you did install Quartus in its default directory right?