"Creating Multiprocessor Nios II Systems Tutorial"

Hi all,

in the "Creating Multiprocessor Nios II Systems Tutorial" Altera document I have:

<div class='quotetop'>QUOTE </div>

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Note that the lower six bits of the exception address are always set to 0x20. Offset 0x0 is where Nios II must run its reset code, so the exception address must be placed elsewhere. The offset of 0x20 is chosen because it corresponds to one instruction cache line. The 0x20 bytes of reset code initializes the instruction cache, and then branches around the exception section to the system startup code.[/b]

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If my system boots from flash,so I have my reset address in flash, and my program and data memory are in SRAM, do I have to set ox20 offset for the exception address in SRAM?