Honored Contributor
Honored Contributorclancy,
I have to correct my statement: My design was created with Quartus 4.1, then updated to Quartus 4.2. At this time I've added this 8-bit peripheral and detected this malfunction. But installing the new SP1 didn't solve the problem. thomas, no, 'DSP' isn't an avalon master , it is one of several slave periherals all sharing avalon bus signals as it is done by the SDRAM controller. One special property of 'DSP' is, that it is an memory-type peripheral, using dynamic bus sizing. This is done to access TI-DSPs over their HPI-8 interface in order to read their internal 16-Bit data. In the meantime Altera is looking for a solution. Results are posted soon. Thanks for your help. Mike
