Constraining Nios Design

I highly recommend that link to Rysc's wiki page on TQ Daixiwen posted.

In general having only one output and one input constraint for your I/O will not provide enough information. For outputs I use the device setup and hold requirements of the off-chip device along with board skews and other things that need to be in the equation. Inputs should be based on the clock-to-out time of the off-chip device as well.

To answer your question about the '2' that should be based on the Tsu, Th, Tco as well as board delays (and skews). The delays should reference a clock so whatever off-chip clock you use for the SSRAM is the one that you want to make those constraints relative to. This should become more clear once you read Rysc's document.