Honored Contributor
Honored ContributorThanks Ganfonz,
One issue is that the data structures that NIOS II is reading from the host memory are defined in legacy source code that is ported ATM -> NIOS II and everything would be great if the 128 bit HIP didn't crash on byte reads . Since the NIOS II fetches a workload of IO control blocks from the host memory and never writes to the descriptors .... I hacked the RTL to force the TXS port byte enables to always perform atleast 4 byte reads..... Image of RTL below which is fairly simple ... test code indicates byte reads with the expected byte returned and no NIOS II hangs ... exerciser is now up and running and I will move to Stratix V 256 and DMA design to get back byte and two byte support. Still not sure how to add the CRA translation. Thanks, Bob.
