Altera_Forum
Honored Contributor
11 years agoConfiguration layout of EPCS ?
Hi, this is my first post here ....:oops:
I would like to understand the layout of the data stored in the EPCS configuration flash. I cannot find clear information in the documentation. The doc "Advanced Boot Copier Example" helps because it states that the nios software image (boot record) has following layout: 4 bytes : length of data 4 bytes : destination of data But what is the format of the fpga hardware configuration ? Looking at the EPCS bootloader source code i understand that the first 4 bytes (at the flash address 0x00) are 0x56565656 , the following 4 bytes are not relevant, and the next 4 bytes are the length of the hardware configuration. But reading my EPCS at 0x00 gives: 0x56565656 0xFFFF0F6C 0xFFFFBFEE so 0xFFFFBFEE cannot be the length of the configuration ?!?!?!? Also the before mentioned document states that there is a signature "0xa5a5a5a5" which i cannot find anywhere.... I simply want to calculate where the hardware configuration ends in the EPCS :( Someone can help ? Any documents which explain the layout of the epcs clearly ?