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Altera_Forum
Honored Contributor
Honored Contributorcoherent pool kernel parameter
I have a Cyclone V ST system. I'm trying to transfer buffers of memory from the HPS to my FPGA. Since the FPGA needs to use it's DDR memory for other things, I thought I'd get the ARM to alloc...
Altera_ForumHonored Contributor
Honored ContributorWhere are you adding `coherent_pool=` I am also trying to increase this on my Cyclone V SX and I'm not sure how to set that parameter.
