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Altera_Forum
Honored Contributor
15 years agoAny "interrupt level" register only shows which interrupts are enabled/masked, this will change if software disables interrupts (splfoo(), splx()). However, since writing to the mask register is expensive (it may take 500ns on a 3Ghz x86 cpu!) the OS may not actually mask the interupt, but allow it to happen and then disable it in the interrupt entry code if one actually happens (calling the ISR later when it is unmasked).
The cpu will globally disable interrupts on interrupt entry. but it is quite common for the OS to re-enable them while the ISR runs. The cpu state then doesn't directly contain any information about whether the code is an ISR. This means you need to use something that the OS does during ISR entry. If the cpu is switched to an interrupt stack, then the range of the stack pointer can be used. If an alternate register set is used, then it may be possible to detect that.