clock consultation

greetings

hi guys

am having an assignment which it basically a car park machine

it has 4 inputs

which is fifty , twenty, ten, ticket

and i need to detect the input and deduct it from an amount of 1.50

so basically i made the design for the stages

and the decoder to view it in four 7-seg bcd

which starts with

insert ticket

then remove ticket

then the 1.50 to check the input of the user

and heres my problem comes

when i apply the code in de1 altera board

the 7-seg doesn't show the first two stages it goes straight away to the 1.50 stage , that happens due to the clock is so fast

even the inputs, lets say i pressed the input 50 the whole process can be done with single press

and am using 50MHZ clock

so i tried to use a clock divider code to reduce it to 1HZ

but it seems that the problem is still there

so is there any way that i can slow the clock so the first two stages can be shown to the user

---------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity clk200 is

Port (

clk_in : in STD_LOGIC;

rst1 : in STD_LOGIC;

clk_out: out STD_LOGIC

);

end clk200;

architecture Behavioral of clk200 is

signal temporal: STD_LOGIC;

signal counter : integer range 0 to 49999999 := 0;

begin

frequency_divider: process (rst1, clk_in) begin

if (rst1 = '1') then

temporal <= '0';

counter <= 0;

elsif rising_edge(clk_in) then

if (counter = 49999999) then

temporal <= NOT(temporal);

counter <= 0;

else

counter <= counter + 1;

end if;

end if;

end process;

clk_out <= temporal;

end Behavioral;

--------------------------------------------------------------------

what i need is method that slow down the clock to the lowest

thank