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Altera_Forum's avatar
Altera_Forum
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9 years ago

Check FPGA / bridges before accessing them

I want to access the switches on the tersIC DE0-Naoo-SoC board from Linux. I load the appropriate FPGA and access the LW bridge (with a c program). Everything works fine. But if, due to eg. mis...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

This sounds like a design bug. Do you have any idea, why the the system hangs up? The only reasons i had so far are:

  • unconfigured FPGA

  • missing bridge in design

  • FPGA Design in reset, or missing clock

  • wrong handled waitrequest in design

  • timing issue

If you have several designs you could identify them with the GPI Pins from the HPS. There is no risk of hanging up.