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Altera_Forum's avatar
Altera_Forum
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9 years ago

Changing HPS SDRAM parameters in Qsys need to rebuild the whole FPGA

I am investigating a issue with HPS SDRAM. What i am doing here is changing some HPS SDRAM parameter in Qsys and recompile HPS.

My question is do i need to rebuild the whole FPGA to make the HPS change active?

If not, then it will save us lots of time for debugging.

Thank you.

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    If I am not mistaken, you only need to regenerate the Qsys component --> that will regenerate the hardware-software handoff files (including the calibration needed for the HPS SDRAM). Then it is a matter of updating the preloader with the latest changes... (again, assuming you are using the bsp-editor tool to generate the preloader that calibrates the SDRAM)

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    Thank you, Sunshine.

    That is my guess too. Yes, i am using bsp-editor to update preloader.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    No, I tried. If I just regen the HPS in Qsys, but do not recompile the whole FPGA, it turned out the hps_isw_handoff files are not updated at all....