Forum Discussion
Altera_Forum
Honored Contributor
19 years agoHi mountain8848,
I am currently making some performance tests on the cal_uart. As you said, there is a (small) performance gain when using the cal_uart but it is not big. I will start modifying the HDL code of the uart to generate the interrupt when the FIFO is half full or 75% full, I will post the results here as soon as it is done. Regarding the post of the files in the 'Post your own IP' section, you should be careful of where the SOPC builder component comes from...do we have all rights on it ? From what I know it is not officially released and it comes from someone inside Altera. Maybe you know more than I do about it, but I would not dare positng it without the authorization of the initial author (that I don't know...). Anyway, lots of thanks for your help, Best regards, Pierre-Olivier